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1 HD66410 (ram-provided 128-channel driver for dot-matrix graphic lcd) ade-207-298(z) '99.9 rev. 0.0 description the HD66410 drives and controls a dot-matrix graphic lcd using a bit-mapped display method. it provides a highly flexible display through its on-chip display ram, in which each bit of data can be used to turn on or off one dot on the lcd panel. a single HD66410 can display a maximum of 128 33 dots using its powerful display control functions. it features 24-channel annunciator output operating with 1/3 duty cycle that is available even during standby modes, which makes it suitable for time and other mark indications. an mpu can access the HD66410 at any time because the mpu operations are asynchronous with the HD66410? system clock and display operations. its low-voltage operation at minimum 2.2v and the standby function provides low power-dissipation, making the HD66410 suitable for small portable device applications. features 4.2-kbits (128 33-bit) bit-mapped display ram 128 33 dots displayed using a single HD66410 ? 8 characters 2 lines (16 16-dot character) ? 21 characters 4 lines (6 8-dot character) annunciator display using dedicated output channels ? maximum of 72 segments displayed with 1/3 duty cycle ? available even during standby modes
HD66410 2 flexible lcd driver configuration ? row output from both sides of an lcd panel ? row output from one side of an lcd panel low power-dissipation suitable for long battery-based operation ? voltage operation: 2.2 to 5.5v ? two standby modes: modes with and without annunciator display on-chip double to quadruple booster versatile display control functions ? display data read/write ? display on/off ? column address inversion according to column driver layout ? vertical display scroll ? blink area select ? read-modify-write 80-system mpu interface through 8-bit asynchronous data bus on-chip oscillator combined with external resistor and capacitor tape carrier package (tcp) ordering information type no. package HD66410ta0 outer lead pitch 300 m m (tcp-239) hcd66410bp die with gold bump
HD66410 3 pin arrangement av3 v5 vcl vch vscl vsch v cc gnd c r cr test1 test0 res cs rs wr rd db0 db1 db2 db3 db4 db5 db6 db7 v cc gnd vci c1+ c1 c2+ c2 c3+ c3 v ee v5 v4 v3 v2 v1 vslo vclo vsho vcho v cc vsh vsl vcsh vcsl av3 com3 com2 com1 seg24 seg11 seg10 x161 x160 x159 x4 x3 x2 x1 seg9 seg4 seg3 seg2 seg1 i/o pins lcd drive signal output pins note: this figure is not drawn to a scale.
HD66410 4 HD66410 pad arrangement chip size : 14.28 2.72mm coordinate : pad center orgin : chip center bump size : 50 70 20 m m dummy pad 1: bump size 70 70 20 m m (typ.) (dmy?, dmy?, dmy?, dmy?) dummy pad 2: bump size 50 70 20 m m (typ.) (dmy? to dmy?0) note 1. the same voltage must be supplied to av3-1 and av3-2, v5-1 and v5-2, vcc-1, vcc-2, vcc-3, and vcc-4, gnd-1, gnd-2 and gnd-3. all (gnd) pads are connected to gnd internally, must be connected to gnd or left open. all (vcc) pads, pad no. 41 to 89, are connected to vcc internally, must be connected to vcc or left open. 2. all dummy pads, dmy1 to dmy40, are not connected to any signal internally. however, these pads are not tested. do not use these pads as a terminal. type code no.122 no.123 no.146 no.147 dmy? no.1 dmy? dmy? no.333 no.312 no.311 dmy?
HD66410 5 HD66410 pad location coordinates pad no. pad name coordinate xy 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 av3-1 (dmy1) vcsl (dmy2) vcsh vsl (dmy3) vsh v cc -1 vcho (dmy4) vsho (dmy5) vclo vslo (dmy6) v1 (dmy7) v2 v3 (dmy8) (dmy9) (dmy10) v4 v5-1 (dmy11) (dmy12) v ee c3 (dmy13) c3+ c2 c2+ c1 c1+ vci gnd-1 (gnd) (gnd) (gnd) (v cc ) (v cc ) (v cc ) (v cc ) (v cc ) (v cc ) (v cc ) (v cc ) (v cc ) (v cc ) ?788 ?708 ?628 ?548 ?468 ?388 ?308 ?228 ?106 ?961 ?881 ?801 ?721 ?641 ?561 ?481 ?401 ?321 ?241 ?161 ?081 ?001 ?894 ?814 ?729 ?524 ?444 ?268 ?178 ?987 ?701 ?621 ?456 ?376 ?088 ?008 ?887 ?767 ?687 ?607 ?527 ?447 ?367 ?287 ?207 ?127 ?047 ?967 ?887 ?807 1056 1056 1056 1056 1056 1056 1056 1056 1056 1056 1056 1056 1056 1056 1056 1056 1056 1020 1020 1020 1020 1020 1056 1056 1056 1069 1069 1069 1069 1069 1076 1076 1076 1076 1069 1069 1069 1069 1069 1069 1202 1202 1202 1202 1202 1202 1202 1202 1202 1202 pad no. pad name coordinate xy 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 (v cc ) (v cc ) (v cc ) (v cc ) (v cc ) (v cc ) (v cc ) (v cc ) (v cc ) (v cc ) (v cc ) (v cc ) (v cc ) (v cc ) (v cc ) (v cc ) (v cc ) (v cc ) (v cc ) (v cc ) (v cc ) (v cc ) (v cc ) (v cc ) (v cc ) (v cc ) (v cc ) (v cc ) (v cc ) (v cc ) (v cc ) (v cc ) (v cc ) (v cc ) (v cc ) (v cc ) (v cc ) (v cc ) (v cc ) v cc -2 db7 db6 db5 db4 db3 db2 db1 db0 rd wr ?727 ?647 ?567 ?487 ?407 ?327 ?247 ?167 ?087 ?007 ?27 ?47 ?67 ?87 ?07 ?27 ?47 ?67 ?87 ?07 ?27 ?7 33 113 193 273 353 433 513 593 673 753 833 913 993 1073 1153 1233 1313 1393 1583 1795 2008 2220 2433 2645 2858 3070 3278 3482 1202 1202 1202 1202 1202 1202 1202 1202 1202 1202 1202 1202 1202 1202 1202 1202 1202 1202 1202 1202 1202 1202 1202 1202 1202 1202 1202 1202 1202 1202 1202 1202 1202 1202 1202 1202 1114 1114 1114 1114 1114 1114 1114 1114 1114 1114 1114 1114 1114 1114 pad no. pad name coordinate xy 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 rs cs res test0 test1 cr r c gnd-2 gnd-3 v cc -3 v cc -4 (dmy14) vsch vscl (dmy15) vch (dmy16) vcl v5-2 (dmy17) av3-2 (dmy18) com3 com2 com1 seg24 seg23 seg22 seg21 seg20 seg19 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 (dmy19) (dmy20) (dmy21) (dmy22) (dmy23) (dmy24) (dmy25) (dmy26) (dmy27) 3686 3890 4094 4298 4477 4685 4893 5102 5360 5440 5711 5791 5975 6055 6135 6215 6295 6375 6455 6535 6663 6744 6925 6925 6925 6925 6925 6925 6925 6925 6925 6925 6925 6925 6925 6925 6925 6925 6925 6925 6925 6925 6925 6925 6925 6925 6754 6674 6594 6514 1114 1114 1114 1114 1114 1114 1114 1114 1114 1114 1114 1114 1114 1114 1114 1114 1114 1114 1114 1114 1114 1114 939 769 689 609 529 449 369 289 209 129 49 ?1 ?11 ?91 ?71 ?51 ?31 ?11 ?91 ?99 ?79 ?59 ?39 ?019 ?139 ?139 ?139 ?139 pad no. pad name coordinate xy 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 x161 x160 x159 x158 x157 x156 x155 x154 x153 x152 x151 x150 x149 x148 x147 x146 x145 x144 x143 x142 x141 x140 x139 x138 x137 x136 x135 x134 x133 x132 x131 x130 x129 x128 x127 x126 x125 x124 x123 x122 x121 x120 x119 x118 x117 x116 x115 x114 x113 x112 6123 6043 5963 5883 5803 5723 5643 5563 5483 5403 5323 5243 5163 5083 5003 4923 4843 4763 4683 4603 4523 4443 4363 4283 4203 4123 4043 3963 3883 3803 3723 3643 3563 3483 3403 3323 3243 3163 3083 3003 2923 2843 2763 2683 2603 2523 2443 2363 2283 2203 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139
HD66410 6 pad no. pad name coordinate xy 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 x111 x110 x109 x108 x107 x106 x105 x104 x103 x102 x101 x100 x99 x98 x97 x96 x95 x94 x93 x92 x91 x90 x89 x88 x87 x86 x85 x84 x83 x82 x81 x80 x79 x78 x77 2123 2043 1963 1883 1803 1723 1643 1563 1483 1403 1323 1243 1163 1083 1003 923 843 763 683 603 523 443 363 283 203 123 43 ?7 ?17 ?97 ?77 ?57 ?37 ?17 ?97 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 pad no. pad name coordinate xy 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 x76 x75 x74 x73 x72 x71 x70 x69 x68 x67 x66 x65 x64 x63 x62 x61 x60 x59 x58 x57 x56 x55 x54 x53 x52 x51 x50 x49 x48 x47 x46 x45 x44 x43 x42 ?77 ?57 ?37 ?17 ?97 ?077 ?157 ?237 ?317 ?397 ?477 ?557 ?637 ?717 ?797 ?877 ?957 ?037 ?117 ?197 ?277 ?357 ?437 ?517 ?597 ?677 ?757 ?837 ?917 ?997 ?077 ?157 ?237 ?317 ?397 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 pad no. pad name coordinate xy 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 x41 x40 x39 x38 x37 x36 x35 x34 x33 x32 x31 x30 x29 x28 x27 x26 x25 x24 x23 x22 x21 x20 x19 x18 x17 x16 x15 x14 x13 x12 x11 x10 x9 x8 x7 ?477 ?557 ?637 ?717 ?797 ?877 ?957 ?037 ?117 ?197 ?277 ?357 ?437 ?517 ?597 ?677 ?757 ?837 ?917 ?997 ?077 ?157 ?237 ?317 ?397 ?477 ?557 ?637 ?717 ?797 ?877 ?957 ?037 ?117 ?197 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 ?139 pad no. pad name coordinate xy 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 x6 x5 x4 x3 x2 x1 (dmy28) (dmy29) (dmy30) (dmy31) (dmy32) (dmy33) (dmy34) (dmy35) (dmy36) (dmy37) (dmy38) (dmy39) (dmy40) seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 (dmy-a) (dmy-b) (dmy-c) (dmy-d) ?277 ?357 ?437 ?517 ?597 ?677 ?935 ?935 ?935 ?935 ?935 ?935 ?935 ?935 ?935 ?935 ?935 ?935 ?935 ?927 ?927 ?927 ?927 ?927 ?927 ?927 ?927 ?927 ?927 6925 6925 ?935 ?139 ?139 ?139 ?139 ?139 ?139 ?018 ?38 ?58 ?78 ?98 ?18 ?38 ?58 ?78 ?98 ?18 ?38 ?8 99 179 259 339 419 499 579 659 739 927 1114 ?139 ?139
HD66410 7 pin description pin name number of pins i/o connected to description v cc , gnd 5 power supply v cc : +2.2 to +5.5v, gnd: 0v vci 1 power supply inputs voltage to the booster to generate the base of the lcd drive voltages (v ee ); must be below v cc . vci: 0 to +3.6v. av3 2 power supply supplies power to the internal annunciator drivers to generate the annunciator drive voltages using av3 and v cc . v cc ?v3: 0 to 3.6v; must be above gnd. v ee 1 booster capacitors and v5 boosts and outputs the voltage input to the vci pin; must be connected to the booster capacitors and v5 pin. v5 2 v ee , resistive divider power supply for lcd driving circuit. supplies several levels of power to the internal lcd drivers for dot-matrix display; must be connected to the v ee pin. v1, v2, v3, v4 4 resistive divider supplies several levels of power to the internal lcd drivers for dot-matrix display; must be applied with the appropriate level of bias for the lcd panel used. c1+ to c3+, c1?to c3 6 booster capacitor must be connected to external capacitors according to the boosting ratio. vsho, vslo 2 o vsh, vsl, vcsh, vcsl, (vsch, vscl) output voltage to be supplied to the internal column drivers. vcho, vclo 2 o vch, vcl, vcsh, vcsl, (vsch, vscl) output voltage to be supplied to the internal row drivers. vsh, vsl 2 i vsho, vslo input voltage to be supplied to internal drivers x17 to x128. vch, vcl 2 i vcho, vclo input voltage to be supplied to internal drivers x145 to x160. vcsh, vcsl 2 i vcho, vclo, vsho, vslo input voltage to be supplied to internal drivers x1 to x16. vsch, vscl 2 i vcho, vclo, vsho, vslo input voltage to be supplied to internal drivers x129 to x144. c, r, cr 3 i, i/o oscillator resistor and capacitor must be connected to external capacitors and resistors when using r-c oscillation. when using an external clock, it must be input to the cr pin. res 1 i resets the lsi internally when driven low. cs 1 i mpu selects the lsi, specifically internal registers (index and data registers) when driven low. rs 1 i mpu selects one of the internal registers; selects the index register when driven low and data registers when driven high. wr 1 i mpu inputs write strobe; allows a write access when driven low.
HD66410 8 pin name number of pins i/o connected to description rd 1 i mpu inputs read strobe; allows a read access when driven low. db7 to db0 8 i/o mpu 8-bit three-state bidirectional data bus; transfers data between the HD66410 and mpu through this bus. x1 to x16, x129 to x144 32 o liquid crystal display output column or row drive signals; either column or row can be selected by programming. x17 to x128 112 o liquid crystal display output column drive signals. x145 to x161 17 o liquid crystal display output row drive signals. com1 to com3 3 o liquid crystal display output row drive signals for annunciator display; available even during standby modes. can operate statically or with 1/3 duty cycle. seg1 to seg24 24 o liquid crystal display output column drive signals for annunciator display; available even during standby modes. test0 1 i gnd tests the lsi; must be grounded. test1 1 o tests the lsi; must be left unconnected.
HD66410 9 register list index register control register 1 control register 2 x address register y address register display memory access register display start raster register blink register 1 blink register 2 blink start raster register blink end raster register reserved reserved reserved reserved reserved reserved annunciator display data register 1 annunciator display data register 2 annunciator display data register 3 annunciator display data register 4 annunciator display data register 5 annunciator display data register 6 annunciator display data register 7 annunciator display data register 8 annunciator display data register 9 annunciator blink register 1 annunciator blink register 2 annunciator blink register 3 reserved reserved reserved reserved w w w w w r/w w w w w w w w w w w w w w w w w w d7 bk0 bk8 ic1a ic2a ic3a ic1i ic2i ic3i ic1q ic2q ic3q ip11 ip21 ip31 disp d6 bk1 bk9 ic1b ic2b ic3b ic1j ic2j ic3j ic1r ic2r ic3r ip10 ip20 ip30 stby ya5 d5 st5 bk2 bk10 bsl5 bel5 ic1c ic2c ic3c ic1k ic2k ic3k ic1s ic2s ic3s ib15 ib25 ib35 ir4 pwr ya4 d4 st4 bk3 bk11 bsl4 bel4 ic1d ic2d ic3d ic1l ic2l ic3l ic1t ic2t ic3t ib14 ib24 ib34 ir3 osc rmw xa3 ya3 d3 st3 bk4 bk12 bsl3 bel3 ic1e ic2e ic3e ic1m ic2m ic3m ic1u ic2u ic3u ib13 ib23 ib33 ir2 idty ddty xa2 ya2 d2 st2 bk5 bk13 bsl2 bel2 ic1f ic2f ic3f ic1n ic2n ic3n ic1v ic2v ic3v ib12 ib22 ib32 ir1 cnf inc xa1 ya1 d1 st1 bk6 bk14 bsl1 bel1 ic1g ic2g ic3g ic1o ic2o ic3o ic1w ic2w ic3w ib11 ib21 ib31 ir0 adc blk xa0 ya0 d0 st0 bk7 bk15 bsl0 bel0 ic1h ic2h ic3h ic1p ic2p ic3p ic1x ic2x ic3x ib10 ib20 ib30 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ir r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 data bits index register bits register symbol register name cs rs 43210 r/w 76543210
HD66410 10 block diagram annunciator display segment driver common/segment driver column driver common/segment driver common driver mpx mpx mpx mpx annunciator display common driver 3-bit shift register annunciator display data register blink control latch 2 latch 1 decoder compa- rator row counter display raster counter m p x 128 33-bit display ram x decoder data buffer y decoder x address counter y address counter blink counter blink registers display start raster register blink start raster register blink end raster register control registers lcd driver power supply selector mpu interface timing generator oscillator lcd driver power supply generator db7?b0 rs wr rd cs test0 test1 vch vsh vcsh vsch vcho vsho v 1 v 3 v 5 vcl vsl vcsl vscl vclo vslo v 2 v 4 v c i v ee c1+ c1 c2 c3 c2+ av3 res cr c rv cc gnd seg1 seg24 x1 x16 x17 x128 x129 x144 x145 x161 com1 com2 com3 level shifter c3+
HD66410 11 system description the HD66410 comprises two kinds of independent lcd drivers: one operating with 1/33 or 1/17 duty cycle for dot-matrix displays and the other operating statically or with 1/3 duty cycle for annunciator displays. these drivers can display a maximum of 128 33 dots (eight 16 16-dot characters 2 lines) on an lcd panel together with a 72-segment annunciator. annunciator display is available even during standby modes, thus enabling constant display such as for a time function. the HD66410 can reduce power dissipation without affecting display because data is retained in the display ram even during standby modes. an lcd system can be configured simply by attaching external capacitors and resistors (figure 1) since the HD66410 incorporates booster circuits. HD66410 x1 to x128 x129 to x161 seg1 to seg24 cs rs rd wr db7 to db0 mpu 8 lcd panel com1 to com3 12:03 figure 1 system block diagram
HD66410 12 mpu interface the HD66410 can interface directly to an mpu through an 8-bit data bus or through an i/o port (figure 2). the mpu can access the HD66410 internal registers independent of internal clock timing. the index register can be directly accessed but the other registers (data registers) cannot. before accessing a data register, its register number must be written to the index register. once written, the register number is held until it is rewritten, enabling the same register to be consecutively accessed without having to rewrite to the register number for each access. an example of a register access sequence is shown in figure 3. HD66410 cs rs rd wr db0?b7 z80 8 a15?0 a0 rd wr d0?7 HD66410 cs rs rd wr db0?b7 h8/325 8 c0 c1 c2 c3 a0?7 b) interface through i/o port decoder a) interface through bus figure 2 8-bit mpu interface examples cs wr rd db7 to db0 rs data data data data data data write index register write data register write data register write index register read data register read data register figure 3 8-bit data transfer sequence
HD66410 13 lcd driver configuration common/segment output assignment: the HD66410 can assign lcd driver output pins x1 to x16 and x129 to x144 to either common or segment output depending on the cnf bit value in control register 1, while x17 to x128 and x145 to x161 are fixed to segment output and common output, respectively. with this function, common output can be positioned on either one side or two sides of an lcd panel. figure 4 shows an example where 33-channel common output is positioned to the right of an lcd panel, with x129 to x144 assigned to row output and x1 to x16 assigned to column output. figure 5 shows an example where 33-channel common output is divided into two and positioned to the right and left of the lcd panel, with x129 to x144 assigned to segment output and x1 to x16 assigned to common output. these assignment are valid in the case of 1/17 display duty. only seventeen x terminals output common signal; unselected signal is output from the rest of terminals which are assigned to row output. lcd HD66410 x161 x145 x128 x129 x144 x17 x16 x1 segment output segment output common output common output a) segment/common output assignment 128-channel segment output 33-channel common output b) system configuration figure 4 common output on right side
HD66410 14 lcd HD66410 x161 x145 x128 x129 x144 x17 x16 x1 common output segment output segment output common output 128-channel segment output 17-channel common output b) system configuration a) segment/common output assignment 16-channel common output figure 5 common output on right and left sides
HD66410 15 x-address inversion according to lcd driver layout: the HD66410 can always display data in address h? on the top left of an lcd panel regardless of where it is positioned with respect to the panel. this is because the HD66410 can invert the positional relationship between display ram addresses and lcd driver output pins by inverting ram addresses. specifically, the HD66410 outputs data in address h? from x1 (x17) when the adc bit in control register 1 is 0, and from x128 (x144) otherwise. here, the scan direction of row output is also inverted according to the situation, as shown in figure 6. note that addresses and scan direction are inverted when data is written to the display ram, and thus changing the adc bit after data has been written has no effect. therefore, hardware control bits such as cnf and adc must be set immediately after reset is canceled, and must not be set while data is being displayed. x1 x2 x3 x4 x5 x6 x7 x8 x128 x127 x126 h'0 lcd panel (a) x161 x129 x17 x18 x19 x20 x21 x22 x23 x24 x144 x143 x142 h'0 lcd panel (b) x161 x145 h'0 x128 x127 x126 x125 x124 x123 x122 x121 x1 x2 x3 lcd panel x129 x161 (c) h'0 x144 x143 x142 x141 x140 x139 x138 x137 x17 x18 x19 lcd panel x145 x161 (d) x16 x1 x1 x16 cnf = 0, adc = 0 (common output on one side; h'0 data from x1) cnf = 1, adc = 0 (common output on both sides; h'0 data from x17) cnf = 0, adc = 1 (common output on one side; h'0 data from x128) cnf = 1, adc = 1 (common output on both sides; h'0 data from x144) figure 6 lcd driver layout and ram addresses (1/33 duty)
HD66410 16 x1 x2 x3 x4 x5 x6 x7 x8 x128 x127 x126 h'0 lcd panel (a) x161 x145 x17 x18 x19 x20 x21 x22 x23 x24 x144 x143 x142 h'0 lcd panel (b) x161 h'0 x128 x127 x126 x125 x124 x123 x122 x121 x1 x2 x3 lcd panel x129 x145 (c) h'0 x144 x143 x142 x141 x140 x139 x138 x137 x17 x18 x19 lcd panel x145 (d) x16 x1 x1 x16 cnf = 0, adc = 0 (common output on one side; h'0 data from x1) cnf = 1, adc = 0 (common output on both sides; h'0 data from x17) cnf = 0, adc = 1 (common output on one side; h'0 data from x128) cnf = 1, adc = 1 (common output on both sides; h'0 data from x144) figure 7 lcd driver layout and ram addresses (1/17 duty)
HD66410 17 display ram configuration and display the HD66410 incorporates a bit-mapped display ram. it has 128 bits in the x direction and 33 bits in the y direction. the 128 bits are divided into sixteen 8-bit groups. as shown in figure 8, data written by the mpu is stored horizontally with the msb at the far left and the lsb at the far right. a display data of 1 turns on (black) the corresponding dot of an lcd panel and 0 turns it off (transparent). the adc bit of control register 1 can control the positional relationship between x addresses of the ram and lcd driver output (figure 9). specifically, the data in address h? is output from x1 (x17) when the adc bit in control register 1 is 0, and from x128 (x144) otherwise. here, data in each 8-bit group is also inverted. because of this function, the data in x address h? can be always displayed on the top left of an lcd panel with the msb at the far left regardless of the lsi is positioned with respect to the panel. lcd panel x161 x160 y0 y1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 db7 (msb) db0 (lsb) display ram x128 x1 x2 x3 x4 x5 x6 x7 x8 figure 8 display ram data and display x1 x128 h'00 h'01 h'1f h'20 lcd drive signal output y addresses x addresses (a) adc = 0 h'0 h'1 h'f msb x1 x128 h'00 h'01 h'1f h'20 lcd drive signal output y addresses x addresses (b) adc = 1 h'f h'e h'0 msb figure 9 display ram configuration
HD66410 18 access to internal registers and display ram access to internal registers by the mpu: the internal registers include the index register and data registers. the index register can be accessed by driving both the cs and rs signals low. to access a data register, first write its register number to the index register with rs set to 0, and then access the data register with rs set to 1. once written, the register number is held until it is rewritten, enabling the same register to be consecutively accessed without having to rewrite to the register number for each access. some data registers contain unused bits; they should be set to 0. note that all data registers except the display memory access register can only be written to. access to display ram by the mpu: to access the display ram, first write the ram address desired to the x address register (r2) and the y address register (r3). then read/write the display memory access register (r4). memory access by the mpu is independent of memory read by the HD66410 and is also asynchronous with the system clock, thus enabling an interface independent of HD66410? internal operations. however, when reading, data is temporarily latched into a HD66410? buffer and then output next time a read is performed in a subsequent cycle. this means that a dummy read is necessary after setting x and y addresses. the memory read sequence is shown in figure 10. x and y addresses are automatically incremented after each memory access according to the inc bit value in control register 2; therefore, it is not necessary to update the addresses for each access. figure 11 shows two cases of incrementing display ram address. when the inc bit is 0, the y address will be incremented up to h?f with the x address unchanged. however, actual memory is valid only within h?0 to h?0; accessing an invalid address is ignored. when the inc bit is 1, the x address will be incremented up to h? with the y address unchanged. after address h?, the x address will return to h?; if more than 16 bytes of data are consecutively written, data will be overwritten at the same address. rs wr rd input data output data undetermined dummy read h'02 [n] h'03 [m] h'04 x address y address data[n,m] data[n,m+1] figure 10 display ram read sequence
HD66410 19 display ram reading by lcd controller: data is read by the HD66410 to be displayed asynchronously with accesses by the mpu. however, because simultaneous access could damaging data in the display ram, the HD66410 internally arbitrates access timing; access by the mpu usually has priority and so access by the HD66410 is placed between accesses by the mpu. accordingly, an appropriate time must be secured (see the given electrical characteristics between two accesses by the mpu). h' 0 h' 01 h' 02 h' 1f h' 20 h' 21 h' 3f h' 1 h' 2 h' e h' f h' 00 valid area invalid area h' 0 h' 01 h' 02 h' 1f h' 1 h' 2 h' e h' f h' 00 h' 20 valid area a) inc = 0 b) inc = 1 figure 11 display ram address increment
HD66410 20 read-modify-write: x- or y-address is incremented after reading from or writing data to the display ram at normal mode. however, x- or y-address is not incremented after reading data from the display ram at read-modify-write mode. the data which is read from the display ram may be modified and written to the same address without resetting the address. data is temporarily latched into a HD66410? buffer and then output next time a read is performed in a subsequent cycle. this means that the dummy read is necessary after every cycle. this sequence is shown in figure 12. start end finish modifying white data read data dummy read set y-address set x-address no address incremented yes figure 12 the flow chart for read-modify-write
HD66410 21 vertical scroll function the HD66410 can vertically scroll a display by varying the top raster to be displayed, which is specified by the display start raster register. figure 13 and 14 show vertical scroll examples. as shown, when the top raster to be displayed is set to 1, data in y address h?0 is displayed on the 33rd raster. to display another frame on the 33rd raster, therefore, data in y address h?0 must be modified after setting the top raster. h'00 h'01 h'02 h'03 h'04 h'05 h'06 h'07 h'08 h'09 h'0a h'1d h'1e h'1f h'20 1 2 3 4 5 6 7 8 9 10 11 30 31 32 33 display raster y address top raster to be displayed = 0 h'01 h'02 h'03 h'04 h'05 h'06 h'07 h'08 h'09 h'0a h'0b h'1e h'1f h'20 h'00 1 2 3 4 5 6 7 8 9 10 11 30 31 32 33 display raster y address top raster to be displayed = 1 h'02 h'03 h'04 h'05 h'06 h'07 h'08 h'09 h'0a h'0b h'0c h'1f h'20 h'00 h'01 1 2 3 4 5 6 7 8 9 10 11 30 31 32 33 display raster y address top raster to be displayed = 2 figure 13 vertical scroll (1/33 duty)
HD66410 22 h'00 h'01 h'02 h'03 h'04 h'05 h'06 h'07 h'08 h'09 h'0a h'1d h'1e h'1f h'20 1 2 3 4 5 6 7 8 9 10 11 30 31 32 33 display raster y address top raster to be displayed = 0 h'01 h'02 h'03 h'04 h'05 h'06 h'07 h'08 h'09 h'0a h'0b h'1e h'1f h'20 h'00 1 2 3 4 5 6 7 8 9 10 11 30 31 32 33 display raster y address top raster to be displayed = 1 h'02 h'03 h'04 h'05 h'06 h'07 h'08 h'09 h'0a h'0b h'0c h'1f h'20 h'00 h'01 1 2 3 4 5 6 7 8 9 10 11 30 31 32 33 display raster y address top raster to be displayed = 2 figure 14 vertical scroll (1/17 duty)
HD66410 23 blink function blinking dot-matrix display area: the HD66410 can blink a specified area on the dot-matrix display. blinking is achieved by repeatedly turning on and off the specified area at a frequency of one sixty-fourth the frame frequency. for example, when the frame frequency is 80 hz, the area is turned on and off every 0.8 seconds. the area to be blinked can be designated by specifying vertical and horizontal positions of the area. the vertical position, or the rasters to be blinked, are specified by the blink start raster register (r8) and blink end raster register (r9). the horizontal position, or the dots to be blinked in the specified rasters, are specified by the blink registers (r6 and r7) in an 8-dot group; each data bit in the blink registers controls its corresponding 8-dot group. the relationship between the registers and blink area is shown in figure 15. setting the blk bit to 1 in control register 2 after setting the above registers starts blinking the designated area. note that since the area to be blinked is designated absolutely with respect to the display ram, it will move along with a scrolling display (figure 16). x8 x16 x24 x32 x40 x48 x56 x64 x72 x80 x88 x96 x104 x112 x120 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 d d d d d d d d d d d d d d d d b b b b b b b b b b b b b b b b 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 r6 r7 blink area blink start raster register (r8) blink end raster register (r9) blink registers lcd x128 figure 15 blink area designation by blink control registers
HD66410 24 display start raster = 0 blink start raster = 0 blink end raster = h'f display start raster = h'5 blink start raster = h'5 blink end raster = h'f figure 16 scrolling blink area
HD66410 25 blinking annunciator display area: the HD66410 can blink up to 18 dots among a maximum of 72 dots on the annunciator display. this function is controlled by a blink controller independent of that for the main dot-matrix display part. the dots to be blinked can be designated by annunciator blink registers 1, 2, and 3, each of which contains two bits to specify a block and six bits to specify dots to be blinked in the specified block (figures 17 and 18). 101001100000111100000000 111000 000000111111110000000000 111000000000000001111100 011111 110001 db5 db4 db3 db2 db1 db0 db5 db4 db3 db2 db1 db0 db5 db4 db3 db2 db1 db0 seg1 seg2 seg3 seg4 seg5 seg6 seg24 com3 com2 com1 annunciator display data registers 1, 4, 7 annunciator blink register 1 ip11 = 0, ip10 = 0 annunciator display data registers 2, 5, 8 annunciator blink register 2 ip21 = 0, ip20 = 1 annunciator display data registers 3, 6, 9 annunciator blink register 3 ip31 = 1, ip30 = 1 block 0 block 1 block 2 block 3 blink dots figure 17 blink area designation by annunciator blink control registers
HD66410 26 ip11 ip21 ip31 ip10 ip20 ip30 ib15 ib25 ib35 ib14 ib24 ib34 ib13 ib23 ib33 ib12 ib22 ib32 ib11 ib21 ib31 ib10 ib20 ib30 db7 db6 db5 db4 db3 db2 db1 db0 ipn1 ipn0 00 blink block block 0 (seg1?eg6) 01 block 1 (seg7?eg12) 10 block 2 (seg13?eg18) 11 block 3 (seg19?eg24) ipn1, ipn0: block select bits (n = 1, 2, 3) annunciator blink register 1 annunciator blink register 2 annunciator blink register 3 figure 18 annunciator blink registers
HD66410 27 power down modes the HD66410 has a standby function providing low power-dissipation, which is initiated by internal register settings. there are two standby modes: in one, all the HD66410 functions are inactive, and in the other, only the annunciator display function is active. in both modes, the internal booster halts but data in the display ram and internal registers except the disp bit is retained. however, only control registers can be accessed during standby modes. in the standby mode with annunciator display, the oscillator does not halt, thus dissipating more power than in the other standby mode. table 1 lists the lcd driver output pin status during standby modes. figure 19 shows the procedure for initiating and canceling a standby mode. note that the cancelation procedure must be strictly followed to protect data in the display ram. table 1 output pin status during standby modes x1 to x161 output v cc (display off) com1 to com3 osc = 0 output v cc (display off) osc = 1 output common signals (display on) seg1 to seg24 osc = 0 output v cc (display off) osc = 1 output segment signals (display on) clear stby bit to 0 (control register 1) wait for power supply to stabilize set disp bit to 1 (control register 1) display starts initiation cancelation set stby bit to 1 (control register 1) clear osc bit to 0 (control register 1) set osc bit to 1 (control register 1) wait for oscillation to stabilize set osc bit to 1 (control register 1) display annunciator? internal operation and booster start oscillation starts oscillation halts internal operation and booster halt standby mode (with annunciator display) standby mode (without annunciator display) no yes figure 19 procedure for initiating and canceling a standby mode
HD66410 28 power on/off procedure figure 20 shows the procedure for turning the power supply on and off. this procedure must be strictly followed to prevent incorrect display because the HD66410 incorporates all power supply circuits . boosting starts boosting halts power on power off clear disp bit to 0 (control register 1) clear pwr bit to 0 (control register 1) turn off power set disp bit to 1 (control register 1) write data to registers and ram as required set idty, cnf, adc, rmw, ddty, inc bits according to the operating mode (control registers 1 and 2) set pwr bit to 1 (control register 1) turn on power (power-on reset) figure 20 procedure for turning power supply on/off
HD66410 29 annunciator display function the HD66410 can display up to 72 dots of annunciator using 24 segment (column) drivers (seg1 to seg24) and three common (row) drivers (com1 to com3). these drivers, independent of the display ram, operate statically or with a 1/3 duty cycle. they are available even during standby modes, where dot-matrix display and the internal booster is turned off, making them suitable for time and other mark indications with reduced power dissipation. the dots to be displayed are designated by annunciator display data registers 1 to 9. for static drive, only display data registers 1, 3, and 7 and row driver com1 are used. a maximum of 18 turned-on dots can be blinked. for details on blinking, see the blink function section. figure 21 shows the relationship between annunciator display data register bits and display positions. in the figure, alphanumerics in the ovals indicate the bit names of annunciator display data registers. data value 1 turns on the corresponding dot on the panel, and data value 0 turns off the corresponding dot. table 2 lists the annunciator display data registers. table 2 annunciator display data register bits register db7 db6 db5 db4 db3 db2 db1 db0 annunciator display data register 1 a0 ic1a ic1b ic1c ic1d ic1e ic1f ic1g ic1h annunciator display data register 2 a1 ic2a ic2b ic2c ic2d ic2e ic2f ic2g ic2h annunciator display data register 3 a2 ic3a ic3b ic3c ic3d ic3e ic3f ic3g ic3h annunciator display data register 4 a3 ic1i ic1j ic1k ic1l ic1m ic1n ic1o ic1p annunciator display data register 5 a4 ic2i ic2j ic2k ic2l ic2m ic2n ic2o ic2p annunciator display data register 6 a5 ic3i ic3j ic3k ic3l ic3m ic3n ic3o ic3p annunciator display data register 7 a6 ic1q ic1r ic1s ic1t ic1u ic1v ic1w ic1x annunciator display data register 8 a7 ic2q ic2r ic2s ic2t ic2u ic2v ic2w ic2x annunciator display data register 9 a8 ic3q ic3r ic3s ic3t ic3u ic3v ic3w ic3x note: only annunciator display data registers 1, 3, and 7 are used for static display. seg1 seg2 ic3a ic2a ic1a ic3b ic2b ic1b seg3 seg4 ic3c ic2c ic1c ic3d ic2d ic1d seg5 seg6 ic3e ic2e ic1e ic3f ic2f ic1f seg7 seg8 ic3g ic2g ic1g ic3h ic2h ic1h seg9 seg10 ic3i ic2i ic1i ic3j ic2j ic1j seg11 seg12 ic3k ic2k ic1k ic3l ic2l ic1l seg13 seg14 ic3m ic2m ic1m ic3n ic2n ic1n seg15 seg16 ic3o ic2o ic1o ic3p ic2p ic1p seg17 seg18 ic3q ic2q ic1q ic3r ic2r ic1r seg19 seg20 ic3s ic2s ic1s ic3t ic2t ic1t seg21 seg22 ic3u ic2u ic1u ic3v ic2v ic1v seg23 seg24 ic3w ic2w ic1w ic3x ic2x ic1x com1 com2 com3 figure 21 annunciator display data and display positions
HD66410 30 oscillator the HD66410 incorporates an r-c oscillator with low power-dissipation, in which the oscillation frequency can be adjusted by appropriate selection of oscillator resistor r f and capacitor c f . the adjusted clock signal is used for system internal circuits; thus, if this oscillator is not used, an appropriate clock signal must be externally input through the cr pin. in this case, the c and r pins must be left unconnected. figure 22 shows oscillator connections. clock and frame frequency the HD66410 generates the frame frequency (lcd drive frequency) by dividing the input clock frequency by 132. the division ratio is the same for all lcd duty cycles. the frame frequency is usually 70 to 90 hz; when the frame frequency is 80 hz, for example, the input clock frequency must be 10.56 khz. cr r c cr HD66410 HD66410 2) when an internal oscillator is used 1) when an external clock is supplied clock the oscillation frequency can be adjusted by varying the oscillator resistor (r f ) and capacitor (c f ). if the r f or c f value is increased, or power supply voltage is decreased, the oscillationfrequency decreases. for the relationship between the r f value, c f value, and oscillationfre quency, see the electrical characteristics section. r f c f r open c open figure 22 oscillator connections
HD66410 31 power supply circuits the HD66410 incorporates a double to quadruple booster to supply power to lcd drivers. the booster is automatically turned off during standby mode, dissipating no power. if the current capacity provided is insufficient for the user system, external power supply circuits are necessary. in this case, the internal power supply can be turned off by register settings. figure 23 shows examples of power supply circuits for different boosting ratios. booster: the internal booster raises the input voltage between v cc and gnd two to four times every raster by turning on the internal power supply with capacitors attached between c1+ and c1? c2+ and c2? c3+ and c3? and to v ee . the booster uses the system clock, and thus the internal oscillator must be operating to activate the booster (if the internal oscillator has been selected to generate the system clock). v ee outputs v cc level when the booster is inactive. c3 c0 c1+ c1 c0 c2+ c2 c0 c3+ c3 gnd vci v cc v ee c1 rb v cc r v1 r v2 2.7r v3 r v4 r r a r th v5 c3 c0 c1+ c1 c0 c2+ c2 c3+ c3 gnd vci v cc v ee c1 c3 c1+ c1 c0 c2+ c2 c3+ c3 gnd vci v cc v ee c1 c0 3 1.0 m f c1 3 2.2 m f a) quadruple boosting c2? c3+: open b) triple boosting c1? c2+, c2? c3+: open c) double boosting thermistor adjust the power supply voltage and capacitance of external capacitors according to the characteristics of the lcd used because the output voltage (v ee ) drop depends on the load current, operation temperature, operation frequency, capacitance of external capacitors, and manufacturing tolerance. refer to the electrical characteristics section for details. adjust the power supply voltage so that the output voltage (v ee ) after boosting will not exceed the absolute maximum rating of the lcd power supply voltage (13v). vci is both a reference voltage and power supply for the booster; it needs to be supplied with at least three times the current consumed by the lcd drivers including the current flowing in the resistive divider. make sure that vci is below v cc . v ee terminal will be in high impedance state when dc/dc converter stops working. in this case v ee level is pulled up to v cc level with external resistors and the voltage supplied to the capacitor c1 is reserved. do not use polarized capacitor to c1. notes: 1. 2. 3. 4. figure 23 power supply circuit examples
HD66410 32 lcd drive voltage power supply levels: to drive the lcd, a 6-level power supply is necessary. these levels can be usually generated by dividing the v cc ?5 power supply using resistive dividers. if the total resistance is small, current consumption increases, and if the total resistance is large, display quality degrades. appropriate resistance should be selected for the user system. brightness adjust: the booster drives liquid crystals with a voltage after raising the voltage supplied to the vci pin two to four times. accordingly, brightness can be adjusted by varying the vci level. attaching a thermister is recommended to vary the voltage according to the thermal characteristics of liquid crystals. annunciator: annunciator has it? own power circuit apart from the main power circuit. four power supply levels are used: these are v cc , av3 and two levels generated by dividing the v cc ?v3 power supply using internal resistive dividers. the level of av3 must be inside of v cc ?nd power supply or connected to gnd unless bright adjust is used. brightness of annunciator can be adjusted by inseriting a resistor into between av3 and gnd. the value of this resistor might be several hundred kilo-ohm because the value of internal resistor is around one mega-ohm. figure 24 shows the power circuit for annunciator. v cc v cc av3 several hundred kilo-ohm 1m iv1 iv2 iv3 stand-by (osc = 0) HD66410t figure 24 power circuit for annunciator
HD66410 33 row/column output switchover: lcd column drivers use v cc , v2, v3, and v5, while row drivers use v cc , v1, v4, and v5. these voltage levels are switched to ac and are output to an lcd panel. since the HD66410 can assign x1 to x16 and x129 to x144 to either row or column output, the power supply connection must be externally changed according to the assignment, which is determined by the cnf bit value in control register 1. the select and deselect levels for row output are temporarily output from the vcho and vclo pins, and the two levels for column output are output from the vsho and vslo pins; these outputs must be connected according to row and column output assignment as shown in figure 25. vch vsch x145?161 x129?144 vcho (row select level) vcl vscl x145?161 x129?144 vclo (row deselect level) vsh vcsh x16?128 x1?15 vsho (column select level) vsl vcsl x16?128 x1?15 vslo (column deselect level) x145?161 x1?15 x145?161 x1?15 x16?128 x129?144 x16?128 x129?144 vcho (row select level) vclo (row deselect level) vsho (column select level) vslo (column deselect level) vch vcsh vcl vcsl vsh vsch vsl vscl a) cnf = 0 b) cnf = 1 figure 25 connection of lcd drive voltage level pins
HD66410 34 reset the low res signal initializes the HD66410, clearing all the bits in the internal registers. during reset, the internal registers cannot be accessed. note that if the reset conditions specified in the electric characteristics section are not satisfied, the HD66410 will not be correctly initialized. in this case, the internal registers of the HD66410 must be initialized by software. initial setting of internal registers: all the internal register bits are cleared to 0. details are listed below. the data in index register is not affected the data in the internal ram are not affected all counters are cleared to zero modes after reset ? normal operation ? oscillator is active ? display is off (including annunciator display) ? booster is not used ? y address of display ram is incremented ? 1/33 duty cycle ? x and y addresses are 0 ? data in address h? is output from the x1 pin ? blink function is inactive initial setting of pins: bus interface pins during reset, the bus interface pins do not accept signals to access internal registers; data is undefined when read. lcd driver output pins during reset, all the lcd driver output pins (x1 to x161, seg1 to seg33, com1 to com3) output v cc -level voltage, regardless of data value in the display ram, turning off the lcd. here, the output voltage is not alternated. note that the same voltage (v cc ) is applied to both column and row output pins to prevent liquid crystals from degrading. booster output pins since the pwr bit in control register 1 is 0 during reset, the booster halts. accordingly, the output state of the v ee pin depends on the value of the booster? external capacitor.
HD66410 35 internal registers the HD66410 has one index register and 22 data registers, all of which can be accessed asynchronously with the internal clock. all the registers except the display memory access register are write-only. accessing unused bits or addresses affects nothing; unused bits should be set to 0 when written to. index register (ir): the index register (figure 26) selects one of 22 data registers. the index register itself is selected when both the cs and rs signals are low. data bits 7 to 5 are unused; they should be set to 0 when written to. control register 1 (r0): control register 1 (figure 27) controls general operations of the HD66410. each bit has its own function as described below. data bit 7 bit is unused; it should be set to 0 when written to. dsp bit dsp = 1: display on dsp = 0: display off (all lcd driver output pins output v cc level) stby bit stby = 1: internal operation and booster halt; display off stby = 0: normal operation the stby bit does not affect the state of pwr and disp bit. pwr bit pwr = 1: booster active pwr = 0: booster inactive osc bit osc = 1: internal operation and booster halt; oscillator does not halt to provide annunciator display osc = 0: internal operation, booster, and oscillator halt the osc bit is valid only when the stby bit is 1. idty bit idty = 1: annunciator display signals are operating statically idty = 0: annunciator display signals are operating with 1/3 duty cycle cnf bit cnf = 1: row output on both sides of the lcd panel cnf = 0: row output on one side of the lcd panel adc bit adc = 1: data in x address h? is output from x128 or x144; row signals are scanned from x129 to x161. adc = 0: data in x address h? is output from x1 or x17; row signals are scanned from x161 to x129.
HD66410 36 data bit set value 76543210 ir register number figure 26 index register (ir) data bit set value 76543210 r0 disp stby pwr osc idty cnf adc figure 27 control register 1 (r0)
HD66410 37 control register 2 (r1): control register 2 (figure 28) controls general operations of the HD66410. each bit has its own function as described below. data bits 7 to 4 are unused; they should be set to 0 when written to. rmw bit rmw = 1: read-modify-write mode address is incremented only after write access rmw = 0: address is incremented after both write and read accesses ddty bit ddty = 1: 1/17 display duty cycle ddty = 0: 1/33 display duty cycle inc bit inc = 1: x address is incremented for each access inc = 0: y address is incremented for each access blk bit blk = 1: blink function is used blk = 0: blink function is not used the blink counter is reset when the blk bit is set to 0. it starts counting and at the same time initiates blinking when the blk bit is set to 1. x address register (r2): the x address register (figure 29) designates the x address of the display ram to be accessed by the mpu. the set value must range from h? to h?; setting a greater value is ignored. the set address is automatically incremented each time the display ram is accessed; it is not necessary to update the address each time. data bits 7 to 4 are unused; they should be set to 0 when written to. y address register (r3): the y address register (figure 30) designates the y address of the display ram to be accessed by the mpu. the set value must range from h?0 to h?0; setting a greater value is ignored. the set address is automatically incremented each time the display ram is accessed; it is not necessary to update the address each time. data bit 7 is unused; it should be set to 0 when written to.
HD66410 38 data bit set value 76543210 r1 rmw ddty inc blk figure 28 control register 2 (r1) data bit set value 76543210 r2 xa3 xa2 xa1 xa0 figure 29 x address register (r2) data bit set value 76543210 r3 ya3 ya2 ya1 ya0 ya4 ya5 figure 30 y address register (r3)
HD66410 39 display memory access register (r4): the display memory access register (figure 31) is used to access the display ram. if this register is write-accessed, data is directly written to the display ram. if this register is read-accessed, data is first latched to this register from the display ram and sent out to the data bus on the next read; therefore, a dummy read access is necessary after setting the display ram address. display start raster register (r5): the display start raster register (figure 32) designates the raster to be displayed at the top of the lcd panel. varying the set value scrolls the display vertically. the set value must be one less than the actual top raster and range from 0 to 32 for 1/33 duty cycle and from 0 to 16 for 1/17 duty cycle. if the value is set outside these ranges, data may not be displayed correctly. data bits 7 and 6 are unused; they should be set to 0 when written to. blink registers (r6, r7): the blink bit registers (figure 33) designate the 8-bit groups to be blinked. setting a bit to 1 blinks the corresponding 8-bit group. any number of groups can be blinked; setting all the bits to 1 will blink the entire lcd panel. these bits are valid only when the blk bit of control register 2 is 1. data bit set value 76543210 r4 d3 d2 d1 d0 d4 d5 d6 d7 figure 31 display memory access register (r4) data bit set value 76543210 r5 st3 st2 st1 st0 st4 st5 figure 32 display start raster register (r5) data bit set value 76543210 r6 bk4 bk5 bk6 bk7 bk3 bk2 bk1 bk0 set value r7 bk12 bk13 bk14 bk15 bk11 bk10 bk9 bk8 figure 33 blink registers (r6, r7)
HD66410 40 blink start raster register (r8): the blink start raster register (figure 34) designates the top raster in the area to be blinked. the set value must be one less than the actual top raster and range from 0 to 32 for 1/33 duty cycle and from 0 to 16 for 1/17 duty cycle. if the value is set outside these ranges, operations may not be correct. data bits 7 and 6 are unused; they should be set to 0 when written to. blink end raster register (r9): the blink end raster register (figure 35) designates the bottom raster in the area to be blinked. the area to be blinked is designated by the blink registers, blink start raster register, and blink end raster register. the set value must be one less than the actual bottom raster and range from 0 to 32 for 1/33 duty cycle and from 0 to 16 for 1/17 duty cycle. it must also be greater than the value set in the blink start raster register. if an inappropriate value is set, operations may not be correct. data bits 7 and 6 are unused; they should be set to 0 when written to. data bit set value 76543210 r8 bsl3 bsl2 bsl1 bsl0 bsl4 bsl5 figure 34 blink start raster register (r8) data bit set value 76543210 r9 bel3 bel2 bel1 bel0 bel4 bel5 figure 35 blink end raster register (r9)
HD66410 41 annunciator display data registers (a0 to a8): the annunciator display data registers (figure 36) store data for annunciator (icon) display. setting a data bit to 1 turns on the corresponding dot on the lcd panel. annunciator blink registers (a9 to a11): the annunciator blink registers (figure 37) designate bits to be blinked on the annunciator display. for details, see the blink function section. ipn1, ipn0 bits (n = 1, 2, 3) these bits select annunciator blocks to be blinked. ipn1, ipn0 = 0, 0: block 0 is selected (seg1 to seg6) ipn1, ipn0 = 0, 1: block 1 is selected (seg7 to seg12) ipn1, ipn0 = 1, 0: block 2 is selected (seg13 to seg18) ipn1, ipn0 = 1, 1: block 3 is selected (seg19 to seg24) ibn5, ibn0 bits (n = 1, 2, 3) these bits select bits to be blinked in the selected blocks. data bit set value 76543210 a0 ic1e ic1f ic1g ic1h ic1d ic1c ic1b ic1a set value a1 ic2e ic2f ic2g ic2h ic2d ic2c ic2b ic2a set value a2 ic3e ic3f ic3g ic3h ic3d ic3c ic3b ic3a set value a3 ic1m ic1n ic1o ic1p ic1l ic1k ic1j ic1i set value a4 ic2m c2n ic2o ic2p ic2l ic2k ic2j ic2i set value a5 ic3m c3n ic3o ic3p ic3l ic3k ic3j ic3i set value a6 ic1u iic1v iic1w ic1x ic1t iic1s ic1r ic1q set value a7 ic2u ic2v ic2w ic2x ic2t ic2s ic2r ic2q set value a8 ic3u ic3v ic3w ic3x ic3t ic3s ic3r ic3q figure 36 annunciator display data registers (a0 to a8) data bit set value 76543210 a9 ib13 ib12 ib11 ib10 ib14 ib15 ip10 ip11 set value a10 ib23 ib22 ib21 ib20 ib24 ib25 ip20 ip21 set value a11 ib33 ib32 ib31 ib30 ib34 ib35 ip30 ip31 figure 37 annunciator blink registers (a9 to a11)
HD66410 42 absolute maximum ratings item symbol ratings unit notes power supply logic circuit v cc ?.3 to +7.0 v 1 voltage lcd drive circuits v ee v cc ?18.0 to v cc + 0.3 v input voltage 1 vt1 ?.3 to v cc + 0.3 v 1, 2 input voltage 2 vt2 v5 ?0.3 to v cc + 0.3 v 1, 3 operating temperature t opr ?0 to +75 c storage temperature t stg ?5 to +110 c notes: 1. measured relative to gnd. 2. applies to pins cr, db7 to db0, rd , wr , cs , rs, res , test0. 3. applies to pins v1, v2, v3, v4, v5, vsh, vsl, vch, vcl, vsch, vscl, vcsh, vcsl. 4. if the lsi is used beyond its absolute maximum rating, it may be permanently damaged. it should always be used within the limits of its electrical characteristics to prevent malfunction or unreliability.
HD66410 43 electrical characteristics dc characteristics (v cc = 2.2 to 5.5v, gnd = 0v, v cc ?5 = 6 to 15v, ta = ?0 to +75 c) *8 item symbol applicable pins min typ max unit measurement condition notes input leakage current (1) i il1 ? 1 m a vin = v cc to gnd 1 input leakage current (2) i il2 ?0 10 m a vin = v cc to v5 2 driver ?n resistance r on x1 to x161 20 k w i on = 100 m a v cc ?5 = 8v 3 input high voltage v ih1 0.8 v cc ? cc v1 input low voltage v il1 0 0.2 v cc v1 output high voltage v oh db7 to db0 0.8 v cc ? cc vi oh = ?0 m a output low voltage v ol db7 to db0 0 0.2 v cc vi ol = 50 m a current consumption during display i disp ?580 m a 4, 5 current consumption during annunciator display i ann ?730 m a 4, 6 current consumption during standby i stb 0.1 5 m a 4, 7 notes: 1. applies to pins: cs , rs, wr , rd , res , cr, test0, db7 to db0 2. applies to pins: v1, v2, v3, v4, vch, vcl, vsh, vsl, vcsh, vcsl, vsch, vscl 3. indicates the resistance between one pin from x1 to x161 and another pin from v1, v2, v3 and v4. vcho, vclo, vsho, vslo and vch, vcl, vsh, vsl, vcsh, vcsl, vsch, vscl are connected according to the configuration. v1 and v2 should be near v cc level, and v3 and v4 should be near v5 level. all voltage must be within d v. d v is the range within which r on is stable. v1 to v4 levels should keep following condition: v cc 3 v1 3 v2 3 v3 3 v4 3 v5 4. input and output current are excluded. when a cmos input is floating, excess current flows from power supply to the input circuit. to avoid this, v ih and v il must be held to v cc and gnd levels, respectively. the current which flows at resistive divider and lcd are excluded. when the unmolded side of lsi is exposed to light, exess current flows. use under sealded condition. 5. specified under following conditions: internal oscillator is used; rf = 470 k w , cf = 100 pf triple boosting is used; c0 = 1.0 m f, c1 = 2.2 m f v cc = vci = 3.0v, v5 = v ee , av3 = gnd, ta = 25 c checker board is displayed no access from mpu 6. measured when stb bit is 1 and osc bit is 1. internal oscillator is used; rf = 470 k w , cf = 100 pf v cc = 3.0v, av3 = gnd 7. measured when stb bit is 1 and osc bit is 0. v cc = 3.0v, all lcd driving outputs, x1 to x161, output v cc level, so no current is consumed at the resistive divider. 8. specified at +75 c for die products.
HD66410 44 booster characteristics (v cc = 2.2 to 5.5v, gnd = 0v, v cc ?5 = 6 to 15v, ta = ?0 to +75 c) *3 item symbol min. typ max unit measurement condition notes output voltage v ee v cc ?0 v cc ?1 v cc ?2 v 1 input voltage v ci 5.5 v 2 notes: 1. measured when v cc = vci = 3.0v, io (load current) = 0.25 ma, c0 = 1 m f, c1 = 2.2 m f f osc ( oscillation frequency) = 10 khz, and the input voltage is boosted four times. 2. input voltage must be below v cc . keep the voltage which is generated with dc/dc counter below the maximum voltage of v cc ?5. if this restriction is not kept, lsi may be destroyed. 3. specified at +75 c for die products. current consumption current consumption are shown below under various conditions. these values are shown as a reference, and are not guaranteed. current consumption during display 1 250 200 150 100 50 0 2 2.5 3 3.5 4 4.5 5 5.5 6 quadruple double triple [ a] i cc v cc [v] internal booster is used; v cc = vci c0 = 1.0 f, c1 = 2.2 f internal oscillator is used: cf = 100 pf, rf = 470 k v5 = v ee no access from mpu the current whih flows at resistive divider and lcd are excluded. current consumption during display 2 100 80 60 40 20 0 2 2.5 3 3.5 4 4.5 5 5.5 6 [ a] i cc v cc [v] internal triple booster is used; v cc = vci c0 = 1.0 f, c1 = 2.2 f external clock: 10 khz v5 = v ee no access from mpu the current whih flows at resistive divider and lcd are excluded.
HD66410 45 current consumption during display 3 1000 800 600 400 200 0 2 2.5 3 3.5 4 4.5 5 5.5 6 [ a] i cc v cc [v] external power is supplied to v5 internal oscillator is used: cf = 100 pf, rf = 470 k v5 = 10v no access from mpu the current which flows at resistive divider and lcd are excluded. note : when the external power supply is supplied to v5, this voltage must be less than five times v cc current consumption during being accessed form mpu 1000 800 600 400 200 0 2 2.5 3 3.5 4 4.5 5 5.5 6 [ a] i cc v cc [v] internal booster is used: v cc = vci c0 = 1.0 f, c1 = 2.2 f internal oscillator is used: cf = 100 pf, rf = 470 k v5 = v ee writing checker board data oscillation frequency v cc = 3.0v cf = 80pf cf = 100pf cf = 120pf 0 40 30 20 10 0 200 400 600 800 r f (k ) [khz] f osc
HD66410 46 v cc ? v ? v 0.45 (v cc ?5) 0.45 (v cc ?5) v5 v1, v2 v3, v4 figure 38 limitation of v1 to v4 levels pins: db7 to db0 v cc v cc output enable input enable data v cc output enable data v cc pins: cs , rs, wr , rd , res ,test0 input terminal i/o terminal pins: test1 output terminal figure 39 terminal configuration
HD66410 47 ac characteristics 1 (v cc = 2.2 to 4.5v, gnd = 0v, ta = ?0 to +75 c) *3 clock characteristics item symbol min typ max unit notes oscillation frequency f osc 7 10 13 khz cf = 100 pf, rf = 470 k w external clock frequency f cp 7 1020khz external clock duty cycle duty 45 50 55 % external clock fall time t r 0.2 m s external clock rise time t f 0.2 m s mpu interface item symbol min typ max unit notes rd low-level width t wrdl 450 tcyc/2?50 ns 1, 2 rd high-level width t wrdh 450 ns 1 wr low-level width t wwrl 450 tcyc/2?50 ns 1, 2 wr high-level width t wwrh 450 ns 1 address setup time t as 10ns address hold time t ah 10ns data delay time t ddr 360 ns data output hold time t dhr 10ns data setup time t dsw 150 ns data hold time t dhw 10ns mpu interface item symbol min typ max unit notes res low-level width t res 1 ms notes 1. tcyc is a period of the clock. 2. keep these specifications even if cs is high. if these conditions are not kept, display flickering may happen. 3. specified at +75 c for die products.
HD66410 48 ac characteristics 2 (v cc = 4.5v to 5.5v, gnd = 0v, ta = ?0 to +75 c) *3 clock characteristics item symbol min typ max unit notes oscillation frequency f osc 8 11.5 14 khz cf = 100 pf, rf = 470 k w external clock frequency f cp 7 20 khz external clock duty cycle duty 45 50 55 % external clock fall time t r 0.2 m s external clock rise time t f 0.2 m s mpu interface item symbol min typ max unit notes rd low-level width t wrdl 450 tcyc/2?50 ns 1, 2 rd high-level width t wrdh 450 ns 1 wr low-level width t wwrl 450 tcyc/2?50 ns 1, 2 wr high-level width t wwrh 450 ns 1 address setup time t as 10ns address hold time t ah 10ns data delay time t ddr 360 ns data output hold time t dhr 10ns data setup time t dsw 150 ns data hold time t dhw 20ns mpu interface item symbol min typ max unit notes res low-level width t res 1 ms notes 1. tcyc is a period of the clock. 2. keep these specifications even if cs is high. if these conditions are not kept, display flickering may happen. 3. specified at +75 c for die products.
HD66410 49 t wwrh t wrdh t dsw t wwrl rd wr t ah t as t as t dhw t wrdl t ah t dhr t ddr rs, cs db7?b0 figure 40 mpu interface
HD66410 50 cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachi? or any third party? patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third party? rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachi? sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail- safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachi? sales office for any questions regarding this document or hitachi semiconductor products. hitachi, ltd. semiconductor & integrated circuits. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 copyright ?hitachi, ltd., 1998. all rights reserved. printed in japan. hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 049318 tel: 535-2100 fax: 535-1533 url northamerica : http:semiconductor.hitachi.com/ europe : http://www.hitachi-eu.com/hel/ecg asia (singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm asia (taiwan) : http://www.hitachi.com.tw/e/product/sicd_frame.htm asia (hongkong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm japan : http://www.hitachi.co.jp/sicd/indx.htm hitachi asia ltd. taipei branch office 3f, hung kuo building. no.167, tun-hwa north road, taipei (105) tel: <886> (2) 2718-3666 fax: <886> (2) 2718-8180 hitachi asia (hong kong) ltd. group iii (electronic components) 7/f., north tower, world finance centre, harbour city, canton road, tsim sha tsui, kowloon, hong kong tel: <852> (2) 735 9218 fax: <852> (2) 730 0281 telex: 40815 hitec hx hitachi europe ltd. electronic components group. whitebrook park lower cookham road maidenhead berkshire sl6 8ya, united kingdom tel: <44> (1628) 585000 fax: <44> (1628) 778322 hitachi europe gmbh electronic components group dornacher stra? 3 d-85622 feldkirchen, munich germany tel: <49> (89) 9 9180-0 fax: <49> (89) 9 29 30 00 hitachi semiconductor (america) inc. 179 east tasman drive, san jose,ca 95134 tel: <1> (408) 433-1990 fax: <1>(408) 433-0223 for further information write to:

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